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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-02-18 13:32:28 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:12:51 +0200 |
| commit | ef4e87b45b96cce65dc26e3bfb67332c3d4d54e1 (patch) | |
| tree | a8af9a13c3bd554d76a80014e88d4546c9484a65 /src/arch/mips/include | |
| parent | 8cc3a2a467cf44f107a6049fc225d2ba9c85b639 (diff) | |
| download | coreboot-ef4e87b45b96cce65dc26e3bfb67332c3d4d54e1.tar.xz | |
arch/mips: simplify cache operations
Cache operations are simplified by removing assembly
implementation and replacing it with simpler C code.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; caches are properly
invalidated;
BRANCH=none
Change-Id: I0f092660549c368e98c208ae0c991fe6f5a428d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf99849e75813cba865b15af9e110687816e61e4
Original-Change-Id: I965e7929718424f92f3556369d36a18ef67aa0d0
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250792
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/mips/include')
| -rw-r--r-- | src/arch/mips/include/arch/cache.h | 4 | ||||
| -rw-r--r-- | src/arch/mips/include/arch/cpu.h | 7 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index 907505981b..3b89632dcd 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -23,10 +23,6 @@ #include <stddef.h> #include <stdint.h> -#define get_icache_line() __get_line_size($16, 1, 19, 3) -#define get_dcache_line() __get_line_size($16, 1, 10, 3) -#define get_L2cache_line() __get_line_size($16, 2, 4, 4) - #define CACHE_TYPE_SHIFT (0) #define CACHE_OP_SHIFT (2) #define CACHE_TYPE_MASK (0x3) diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 957e427e73..e04621420e 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -106,6 +106,13 @@ do { \ #define read_c0_config1() __read_32bit_c0_register($16, 1) #define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val)) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, (val)) + +#define read_c0_l23taglo() __read_32bit_c0_register($28, 4) +#define write_c0_l23taglo(val) __write_32bit_c0_register($28, 4, (val)) + + #define C0_ENTRYLO_PFN_SHIFT 6 #define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */ #define C0_ENTRYLO_D (0x1 << 2) /* Writeable */ |