diff options
author | Greg Watson <gwatson@lanl.gov> | 2005-10-20 01:44:21 +0000 |
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committer | Greg Watson <gwatson@lanl.gov> | 2005-10-20 01:44:21 +0000 |
commit | 8d4edc2fcd003990228f505ce717c32b45831f2d (patch) | |
tree | 3024ed9def3ae2572c42d45facf5cf7259325f6c /src/arch/ppc/lib | |
parent | 58cb0bf1dfe1fa39760c3edcc68146fe6ed9d474 (diff) | |
download | coreboot-8d4edc2fcd003990228f505ce717c32b45831f2d.tar.xz |
changes to support new ppc arch
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/ppc/lib')
-rw-r--r-- | src/arch/ppc/lib/Config.lb | 4 | ||||
-rw-r--r-- | src/arch/ppc/lib/ppc.c | 49 | ||||
-rw-r--r-- | src/arch/ppc/lib/setup.c | 130 |
3 files changed, 51 insertions, 132 deletions
diff --git a/src/arch/ppc/lib/Config.lb b/src/arch/ppc/lib/Config.lb index e501592683..b174032b8e 100644 --- a/src/arch/ppc/lib/Config.lb +++ b/src/arch/ppc/lib/Config.lb @@ -1,10 +1,10 @@ object c_start.S -object setup.o object pci_ppc_conf1_ops.o object pci_dev.o object timer.o object cpuid.o object cpu.o +object ppc.o object timebase.S object floats.S object div64.S @@ -12,6 +12,6 @@ initobject pci_dev.o initobject printk_init.o initobject timebase.S initobject timer.o -initobject setup.o initobject floats.S initobject div64.S +initobject ppc.o diff --git a/src/arch/ppc/lib/ppc.c b/src/arch/ppc/lib/ppc.c new file mode 100644 index 0000000000..6222536864 --- /dev/null +++ b/src/arch/ppc/lib/ppc.c @@ -0,0 +1,49 @@ +/* Copyright 2000 AG Electronics Ltd. */ +/* This code is distributed without warranty under the GPL v2 (see COPYING) */ + +#include "ppc.h" +#include "ppcreg.h" + +unsigned ppc_getmsr(void) +{ + unsigned result; + __asm__ volatile ("mfmsr %0" : "=r" (result)); + return result; +} + +unsigned ppc_gethid0(void) +{ + unsigned result; + __asm__ volatile ("mfspr %0,1008" : "=r" (result)); + return result; +} + +unsigned ppc_gethid1(void) +{ + unsigned result; + __asm__ volatile ("mfspr %0,1009" : "=r" (result)); + return result; +} + +void ppc_sethid0(unsigned value) +{ + __asm__ volatile ("mtspr 1008,%0" : : "r" (value)); +} + +unsigned ppc_getpvr(void) +{ + unsigned result; + __asm__("mfspr %0, 287" : "=r" (result)); + return result; +} + +void ppc_setmsr(unsigned value) +{ + __asm__ volatile ("mtmsr %0; sync" :: "r" (value)); +} + +void ppc_set1015(unsigned value) +{ + __asm__ volatile ("mtspr 1015,%0" : : "r" (value)); +} + diff --git a/src/arch/ppc/lib/setup.c b/src/arch/ppc/lib/setup.c deleted file mode 100644 index 3e197b37df..0000000000 --- a/src/arch/ppc/lib/setup.c +++ /dev/null @@ -1,130 +0,0 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ - -#include "ppc.h" -#include "ppcreg.h" - -unsigned ppc_getmsr(void) -{ - unsigned result; - __asm__ volatile ("mfmsr %0" : "=r" (result)); - return result; -} - -unsigned ppc_gethid0(void) -{ - unsigned result; - __asm__ volatile ("mfspr %0,1008" : "=r" (result)); - return result; -} - -unsigned ppc_gethid1(void) -{ - unsigned result; - __asm__ volatile ("mfspr %0,1009" : "=r" (result)); - return result; -} - -void ppc_sethid0(unsigned value) -{ - __asm__ volatile ("mtspr 1008,%0" : : "r" (value)); -} - -unsigned ppc_getpvr(void) -{ - unsigned result; - __asm__("mfspr %0, 287" : "=r" (result)); - return result; -} - -void ppc_setmsr(unsigned value) -{ - __asm__ volatile ("mtmsr %0; sync" :: "r" (value)); -} - -void ppc_set1015(unsigned value) -{ - __asm__ volatile ("mtspr 1015,%0" : : "r" (value)); -} - -extern void ppc_init_float_registers(const double *); -/*RODATA static const double dummy_float = 1.0;*/ -static const double dummy_float = 1.0; - -#define HID0_DCACHE HID0_DCE -#define MSR_DATA MSR_DR - -void ppc_setup_cpu(int icache) -{ - int type = ppc_getpvr() >> 16; - int version = ppc_getpvr() & 0xffff; - - if (type == 0xc) - { - if (version == 0x0200) - ppc_set1015(0x19000004); - else if (((version & 0xff00) == 0x0200) && - (version != 0x0209)) - ppc_set1015(0x01000000); - } - if (icache) - { - ppc_sethid0(HID0_NHR | HID0_BHT | HID0_ICE | HID0_ICFI - | HID0_BTIC | HID0_DCACHE); - ppc_sethid0(HID0_DPM | HID0_NHR | HID0_BHT | HID0_ICE - | HID0_BTIC | HID0_DCACHE); - } - else - { - ppc_sethid0(HID0_DPM | HID0_NHR | HID0_BHT | HID0_BTIC - | HID0_DCACHE); - } -#if 1 - /* if (type == 8 || type == 12) */ - { - ppc_setmsr(MSR_FP | MSR_DATA); - ppc_init_float_registers(&dummy_float); - } -#endif -} - -void ppc_enable_dcache(void) -{ - /* - * Already enabled in crt0.S - */ -#if 0 - unsigned hid0 = ppc_gethid0(); - ppc_sethid0(hid0 | HID0_DCFI | HID0_DCE); - ppc_sethid0(hid0 | HID0_DCE); -#endif -} - -void ppc_disable_dcache(void) -{ - unsigned hid0 = ppc_gethid0(); - ppc_sethid0(hid0 & ~HID0_DCE); -} - -void ppc_enable_mmu(void) -{ - unsigned msr = ppc_getmsr(); - ppc_setmsr(msr | MSR_DR | MSR_IR); -} - -void make_coherent(void *base, unsigned length) -{ - unsigned hid0 = ppc_gethid0(); - - if (hid0 & HID0_DCE) - { - unsigned i; - unsigned offset = 0x1f & (unsigned) base; - unsigned adjusted_base = (unsigned) base & ~0x1f; - for(i = 0; i < length + offset; i+= 32) - __asm__ volatile ("dcbf %1,%0" : : "r" (adjusted_base), "r" (i)); - if (hid0 & HID0_ICE) - for(i = 0; i < length + offset; i+= 32) - __asm__ volatile ("icbi %1,%0" : : "r" (adjusted_base), "r" (i)); - } -} |