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| author | Xiang Wang <wxjstz@126.com> | 2018-09-11 15:53:36 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-11 10:56:54 +0000 |
| commit | 4356e09235b911ad0c66f7467e25f6a88e823009 (patch) | |
| tree | a430040c577e63efdf37bbe07e7da32fe2414728 /src/arch/riscv/Makefile.inc | |
| parent | a08475e9abe48393453560a7bdd9ffc040be7845 (diff) | |
| download | coreboot-4356e09235b911ad0c66f7467e25f6a88e823009.tar.xz | |
riscv: add physical memory protection (PMP) support
These codes are written by me based on the privileged instruction set.
I tested it by qemu/riscv-probe.
Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28569
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/Makefile.inc')
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index a2bd763cd9..d1354e1249 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -54,6 +54,7 @@ bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += misc.c +bootblock-y += pmp.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -82,6 +83,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c romstage-y += stages.c romstage-y += misc.c +romstage-y += pmp.c romstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -120,6 +122,7 @@ ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += payload.S +ramstage-y += pmp.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ |