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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-08-22 19:37:16 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2016-08-23 23:47:01 +0200 |
| commit | 857e33e27f1feeec328ae8be5ad61ee51b75e4ec (patch) | |
| tree | dd743b4fda0ac4c6f485e56a982fbc50932a4e42 /src/arch/riscv/Makefile.inc | |
| parent | 3965a522c23ea50b1a861b89a8215a524caa35f7 (diff) | |
| download | coreboot-857e33e27f1feeec328ae8be5ad61ee51b75e4ec.tar.xz | |
arch/riscv: Implement the SBI again
Not all SBI calls are implemented, but it's enough to see a couple dozen
lines of Linux boot output.
It should also be noted that the SBI is still in flux:
https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM
Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16119
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/Makefile.inc')
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 718aad9582..4bab459676 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -95,6 +95,7 @@ ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c +ramstage-y += sbi.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ |