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author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-09-30 20:09:58 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-04 09:38:22 +0000 |
commit | 6dff3fdd403b57cd9ebaa9518a2e51e42e18e6ff (patch) | |
tree | 341bf43a541c9e6300f38a23fcc488753d69cfa6 /src/arch/riscv/Makefile.inc | |
parent | 02820ca1862fdf7078aa0749d3f2ef5c80b0daba (diff) | |
download | coreboot-6dff3fdd403b57cd9ebaa9518a2e51e42e18e6ff.tar.xz |
arch/riscv: Adjust compiler flags for scan-build
Clang doesn't understand -march=riscv64imac and -mcmodel=medany, so
don't use them when running the clang static analyzer. On the other
hand, __riscv and __riscv_xlen need to be defined in order to select
some macros in src/arch/riscv/include/arch/encoding.h. __riscv_flen
selects the floating-point paths in src/arch/riscv/misaligned.c.
-mabi is moved with -march for consistency.
A complete list of preprocessor definitions on RISC-V can be found at
https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
With this commit, scan-build produces a useful result on RISC-V.
Change-Id: Ia2eb8c3c2f7eb5ddd47db24b8e5fcd6eaf6c5589
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/riscv/Makefile.inc')
-rw-r--r-- | src/arch/riscv/Makefile.inc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 50c1ae69d6..a2bd763cd9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -25,7 +25,12 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) check-ramstage-overlap-regions += stack endif -riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CODEMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) +riscv_flags = -I$(src)/arch/riscv/ +ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) +riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) +else +riscv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64 +endif riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) |