diff options
author | Xiang Wang <wxjstz@126.com> | 2018-10-11 17:30:37 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:03:40 +0000 |
commit | 7c9540ea1d46a776ec92b58f99074f51b430f9bb (patch) | |
tree | dc9b3d25062791f40edd72ddcccaa3dd0171b85c /src/arch/riscv/Makefile.inc | |
parent | c85f9c589726caba41970d5fbdadd8a147dd7956 (diff) | |
download | coreboot-7c9540ea1d46a776ec92b58f99074f51b430f9bb.tar.xz |
riscv: add support smp_pause / smp_resume
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.
Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/arch/riscv/Makefile.inc')
-rw-r--r-- | src/arch/riscv/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index d1354e1249..eacf32acfd 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -53,6 +53,7 @@ bootblock-y += misaligned.c bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c +bootblock-y += smp.c bootblock-y += misc.c bootblock-y += pmp.c bootblock-y += \ @@ -84,6 +85,7 @@ romstage-y += boot.c romstage-y += stages.c romstage-y += misc.c romstage-y += pmp.c +romstage-y += smp.c romstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -119,6 +121,7 @@ ramstage-y += misaligned.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c +ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += payload.S |