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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-06-21 19:37:03 +0200
committerMartin Roth <martinroth@google.com>2016-06-28 18:52:37 +0200
commit719f9b53898bffa52395a1e25b616432eef6ff57 (patch)
tree968da7bbe0dedb6c8916197c3205f328bf7548ab /src/arch/riscv/bootblock.S
parent4f7d329caaa99814a2383872025ca1757cf4fbad (diff)
downloadcoreboot-719f9b53898bffa52395a1e25b616432eef6ff57.tar.xz
arch/riscv: Move _start to the beginning of the bootblock
The different entry points (0x100, 0x140, ...), which were defined in the RISC-V Privileged Specification 1.7, aren't used anymore. Instead the Spike bootrom jumps at the start of our image, and traps are handled through mtvec. Change-Id: I865adec5e7a752a25bac93a45654ac06e27d5a8e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15283 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/bootblock.S')
-rw-r--r--src/arch/riscv/bootblock.S15
1 files changed, 1 insertions, 14 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index e75e1ca407..07d68ab851 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -17,20 +17,7 @@
#include <arch/encoding.h>
.section ".text._start", "ax", %progbits
-// Maybe there's a better way.
-# machine mode handler when in supervisor mode
-.space 0x140
-supervisor_machine_handler:
- j supervisor_trap_entry
-
-# handler for when
-.space 0x7c
-.globl machine_handler
-machine_handler:
-# call trap_handler
- j trap_entry
-
-.space 0x3c
+
.globl _start
_start: