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| author | Thaminda Edirisooriya <thaminda@google.com> | 2015-08-26 15:39:16 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-09-16 17:17:11 +0000 |
| commit | a47738d10f9c6e4d14ffbd35a01c6e70c2c494e5 (patch) | |
| tree | f760398a99d0a794f206268fc5e05c0b25ea0019 /src/arch/riscv/bootblock.S | |
| parent | ebf623b53caea9fb1781668143fb3dc9fff08f6a (diff) | |
| download | coreboot-a47738d10f9c6e4d14ffbd35a01c6e70c2c494e5.tar.xz | |
riscv-memlayout: fix existing memlayout issues, add sbi interface
Existing memlayout code placed sections in overlapping areas, and would
overwrite the payload if it was large enough. Update memlayout.ld in
src/mainboard/emulation/spike-riscv to represent the spike emulator, and
add sbi interface which now has room into src/arch/riscv/bootblock.S.
Add utility code to qemu-riscv, but emulator itself has yet to be
updated to new ISA and as such should not be used.
Update Makefile to include all the files necessary for sbi interface.
Clean up unused include in src/arch/riscv/include/atomic.h and
whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
Fixed whitespace issues in spike_util.c
Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/bootblock.S')
| -rw-r--r-- | src/arch/riscv/bootblock.S | 108 |
1 files changed, 94 insertions, 14 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index a26b144458..4caeea6000 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,7 +1,7 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2013Google Inc. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,34 +22,112 @@ .section ".text._start", "ax", %progbits // Maybe there's a better way. -.space 0x200 +# machine mode handler when in supervisor mode +.space 0x140 +supervisor_machine_handler: + j supervisor_trap_entry + +# handler for when +.space 0x7c +.globl machine_handler +machine_handler: +# call trap_handler + j trap_entry + +.space 0x3c .globl _start _start: // pending figuring out this f-ing toolchain. Hardcode what we know works. -// la sp, 0x4ef0 // .stacktop -// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv - la sp, 0x7FF00 // stack start + stack size + la sp, 0x80FFF0 // stack start + stack size - // make room for HLS + # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - + csrr a0, mhartid + call hls_init //poison the stack - la t1, 0x40000 + la t1, 0x800000 li t0, 0xdeadbeef sd t0, 0(t1) -// la gp, _gp + la t0, exception_handler + csrw stvec, t0 # clear any pending interrupts -#if __GNUC__ < 5 - csrwi clear_ipi, 0 -#else csrwi sip, 0 -#endif + # set up the mstatus register for VM + call mstatus_init call main +.=0x2000 + .space 0x800 +# sbi interface lives here + +# hart_id +.align 5 +li a7, 0 +ecall +ret + +# num_harts +.align 4 +li a0, 1 +ret + +# query_memory +.align 4 +li a7, 8 +ecall +ret + +# console_putchar +.align 4 +li a7, 1 +ecall +ret + +# send_device_request +.align 4 +li a7, 2 +ecall +ret + +# receive_device_response +.align 4 +li a7, 3 +ecall +ret + +# send ipi +.align 4 +li a7, 4 +ecall +ret + +# clear ipi +.align 4 +li a7, 5 +ecall +ret + +# timebase +.align 4 +li a0, 10000000 # temporary, we should provide the correct answer +ret + +# shutdown +.align 4 +li a7, 6 +ecall + +# set_timer +.align 4 +li a7, 7 +ecall +ret + +# end of SBI trampolines .=0x4000 .stack: .align 8 @@ -59,7 +137,9 @@ _start: .align 3 .stack_size: .quad 0xf00 - +.globl test_trap +exception_handler: + call trap_handler reset: init_stack_loop: |