riscv: Add a bandaid for the new toolchain

After I did a new toolchain build, I found the
the mhartid register value is wrong for Spike.
The docs seem to agree with Spike, not the
code the toolchain produces?

Until such time as the bitstreams and toolchain can find
a way to agree, just hardcode it. We've been playing this game
for two years now so this is hardly a new approach.

This is intentionally ugly because we really need the
toolchains and emulators and bitstreams to sync up,
and that's not happening yet. Lowrisc
allegedly implements the v1.9 spec but it's PTEs are clearly
1.7. Once it all settles down we can just use constants
supplied by the toolchain.

I hope the syncup will have happened by the workshop in November.

This gets spike running again.

Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17183
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

1 files changed, 5 insertions, 1 deletions

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 63df92bb38..c54c0e235c 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -32,7 +32,11 @@ _start:
 
 	# make room for HLS and initialize it
 	addi sp, sp, -64 // MENTRY_FRAME_SIZE
-	csrr a0, mhartid
+	// Once again, the docs and toolchain disagree.
+	// Rather than get fancy I'll just lock this down
+	// until it all stabilizes.
+	//csrr a0, mhartid
+	csrr a0, 0xf14
 	call hls_init
 
 	# poison the stack