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author | Ronald G. Minnich <rminnich@gmail.com> | 2014-11-26 19:25:47 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2014-12-01 19:06:43 +0100 |
commit | e0e784a456c4d64e5e88ce578371fe6c538db559 (patch) | |
tree | 7557a07ab68659eaf81ac50fc860a288055e0845 /src/arch/riscv/bootblock_simple.c | |
parent | 796fe068d3c47f873b82c65cc0591f88f87b0a85 (diff) | |
download | coreboot-e0e784a456c4d64e5e88ce578371fe6c538db559.tar.xz |
Add UCB RISCV support for architecture, soc, and emulation mainboard..
Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/riscv/bootblock_simple.c')
-rw-r--r-- | src/arch/riscv/bootblock_simple.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/arch/riscv/bootblock_simple.c b/src/arch/riscv/bootblock_simple.c new file mode 100644 index 0000000000..d8339d1f76 --- /dev/null +++ b/src/arch/riscv/bootblock_simple.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <bootblock_common.h> +#include <arch/cache.h> +#include <arch/hlt.h> +#include <arch/stages.h> +#include <arch/exception.h> +#include <cbfs.h> +#include <console/console.h> + +static int boot_cpu(void) +{ + /* + * FIXME: This is a stub for now. All non-boot CPUs should be + * waiting for an interrupt. We could move the chunk of assembly + * which puts them to sleep in here... + */ + return 1; +} + +void main(void) +{ + const char *stage_name = CONFIG_CBFS_PREFIX"/romstage"; + void *entry = NULL; + + /* Globally disable MMU, caches, and branch prediction (these should + * be disabled by default on reset) */ + dcache_mmu_disable(); + + /* + * Re-enable icache and branch prediction. MMU and dcache will be + * set up later. + * + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + + if (boot_cpu()) { + //bootblock_cpu_init(); + //bootblock_mainboard_init(); + } + +#ifdef CONFIG_BOOTBLOCK_CONSOLE + console_init(); + exception_init(); +#endif + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); + + printk(BIOS_SPEW, "stage_name %s, entry %p\n", stage_name, entry); + + if (entry) stage_exit(entry); + hlt(); +} |