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authorThaminda Edirisooriya <thaminda@google.com>2015-07-29 17:43:20 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-08-09 19:56:52 +0200
commit8fad21db54d1435333f832767fb65312db103eb2 (patch)
tree108112f06e092b01695d7f045aec981a7c3be32a /src/arch/riscv/include/atomic.h
parentd7eb0cbf9ad27d667d68dae449226b5b789f3db2 (diff)
downloadcoreboot-8fad21db54d1435333f832767fb65312db103eb2.tar.xz
riscv-spike: support for Spike emulation of riscv
Spike support: QEMU RISCV is broken, and the maintainers at Berkeley are working on it, but at the moment spike is the only way to test on riscv. Add support for spike console output for debugging. Privileged ISA: Update to privileged ISA in RISCV (machine, supervisor, hypervisor, user modes) broke exisitng RISCV asm, and bootblock.S was updated to match the new spec. Clean old assembly [pg: things build with gcc 4.9 now, but don't expect them to work. Hardcoding register names into the assembler language may not be the smartest idea of the RISCV folks.] Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/riscv/include/atomic.h')
-rw-r--r--src/arch/riscv/include/atomic.h73
1 files changed, 73 insertions, 0 deletions
diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h
new file mode 100644
index 0000000000..8d7295d930
--- /dev/null
+++ b/src/arch/riscv/include/atomic.h
@@ -0,0 +1,73 @@
+// See LICENSE for license details.
+
+#ifndef _RISCV_ATOMIC_H
+#define _RISCV_ATOMIC_H
+
+//#include "config.h"
+#include <arch/encoding.h>
+
+#define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)
+#define enable_irqrestore(flags) set_csr(sstatus, (flags) & SSTATUS_IE)
+
+typedef struct { int lock; } spinlock_t;
+#define SPINLOCK_INIT {0}
+
+#define mb() __sync_synchronize()
+#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
+#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
+
+#ifdef PK_ENABLE_ATOMICS
+# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
+# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
+# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
+#else
+# define atomic_add(ptr, inc) ({ \
+ long flags = disable_irqsave(); \
+ typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
+ *(volatile typeof(ptr))(ptr) = res + (inc); \
+ enable_irqrestore(flags); \
+ res; })
+# define atomic_swap(ptr, swp) ({ \
+ long flags = disable_irqsave(); \
+ typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \
+ *(volatile typeof(ptr))(ptr) = (swp); \
+ enable_irqrestore(flags); \
+ res; })
+# define atomic_cas(ptr, cmp, swp) ({ \
+ long flags = disable_irqsave(); \
+ typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
+ if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \
+ enable_irqrestore(flags); \
+ res; })
+#endif
+
+static inline void spinlock_lock(spinlock_t* lock)
+{
+ do
+ {
+ while (atomic_read(&lock->lock))
+ ;
+ } while (atomic_swap(&lock->lock, -1));
+ mb();
+}
+
+static inline void spinlock_unlock(spinlock_t* lock)
+{
+ mb();
+ atomic_set(&lock->lock,0);
+}
+
+static inline long spinlock_lock_irqsave(spinlock_t* lock)
+{
+ long flags = disable_irqsave();
+ spinlock_lock(lock);
+ return flags;
+}
+
+static inline void spinlock_unlock_irqrestore(spinlock_t* lock, long flags)
+{
+ spinlock_unlock(lock);
+ enable_irqrestore(flags);
+}
+
+#endif