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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-10-28 00:25:02 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2016-11-07 16:47:49 +0100 |
| commit | 99f2f113ec397dd042dcaa23c47123f3def19ebc (patch) | |
| tree | 38b8eb7e1ad90c2d5e2b2bb6ed32ddca99016214 /src/arch/riscv/include | |
| parent | 7ca9b8ae5014a745855296903682ae803235cb35 (diff) | |
| download | coreboot-99f2f113ec397dd042dcaa23c47123f3def19ebc.tar.xz | |
riscv: Unify SBI call implementations under arch/riscv/
Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.
TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
payload. It worked as much as before (Linux didn't boot, but it
made some successful SBI calls)
Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/include')
| -rw-r--r-- | src/arch/riscv/include/mcall.h (renamed from src/arch/riscv/include/spike_util.h) | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/mcall.h index 175ee6ce2f..a43b9cf49b 100644 --- a/src/arch/riscv/include/spike_util.h +++ b/src/arch/riscv/include/mcall.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _SPIKE_UTIL_H -#define _SPIKE_UTIL_H +#ifndef _MCALL_H +#define _MCALL_H #include <arch/encoding.h> #include <atomic.h> |