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authorThaminda Edirisooriya <thaminda@google.com>2015-08-26 15:39:16 -0700
committerRonald G. Minnich <rminnich@gmail.com>2015-09-16 17:17:11 +0000
commita47738d10f9c6e4d14ffbd35a01c6e70c2c494e5 (patch)
treef760398a99d0a794f206268fc5e05c0b25ea0019 /src/arch/riscv/include
parentebf623b53caea9fb1781668143fb3dc9fff08f6a (diff)
downloadcoreboot-a47738d10f9c6e4d14ffbd35a01c6e70c2c494e5.tar.xz
riscv-memlayout: fix existing memlayout issues, add sbi interface
Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Add utility code to qemu-riscv, but emulator itself has yet to be updated to new ISA and as such should not be used. Update Makefile to include all the files necessary for sbi interface. Clean up unused include in src/arch/riscv/include/atomic.h and whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld Fixed whitespace issues in spike_util.c Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/atomic.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h
index 8d7295d930..f63f6e1fd9 100644
--- a/src/arch/riscv/include/atomic.h
+++ b/src/arch/riscv/include/atomic.h
@@ -3,7 +3,6 @@
#ifndef _RISCV_ATOMIC_H
#define _RISCV_ATOMIC_H
-//#include "config.h"
#include <arch/encoding.h>
#define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)