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authorXiang Wang <wxjstz@126.com>2019-03-20 12:04:43 +0800
committerPatrick Rudolph <siro@das-labor.org>2019-06-23 12:14:30 +0000
commit3280aa7df266c964e1b354b18fcd3134f310b776 (patch)
tree0d8e4d000160672d7e5d820d6e86c005391cfd19 /src/arch/riscv/include
parentb874ef4925332f16aba1ce85696abfb1da72e0cb (diff)
downloadcoreboot-3280aa7df266c964e1b354b18fcd3134f310b776.tar.xz
riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths
Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/mcall.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index 192d2b4564..d7d67ce33b 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -27,7 +27,7 @@
#endif
/* We save 37 registers, currently. */
-#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)
+#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * __SIZEOF_POINTER__)
#ifndef __ASSEMBLER__