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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2017-09-26 01:44:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-11-07 12:29:08 +0000 |
| commit | 92f0513a0ca8a3d262f3e16f17366a2e517fec74 (patch) | |
| tree | 45bdcd27e7362a5ac028fb7e8076f4420594c90b /src/arch/riscv/include | |
| parent | 0c42cd324018fa921348acbc9f54ba0db764b201 (diff) | |
| download | coreboot-92f0513a0ca8a3d262f3e16f17366a2e517fec74.tar.xz | |
arch/riscv: mprv_read_*: Mark result as earlyclobber
This fixes a case of mstatus corruption, where GCC generated code that
used the same register for the mprv bit and the result.
GCC inline assembly register modifiers are documented here:
https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html
Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/include')
| -rw-r--r-- | src/arch/riscv/include/vm.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 0db5313580..1a8f7ad6e0 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -73,7 +73,7 @@ void flush_tlb(void); "csrs mstatus, %1\n" \ STRINGIFY(insn) " %0, 0(%2)\n" \ "csrc mstatus, %1\n" \ - : "=r"(value) : "r"(mprv), "r"(p) : "memory" \ + : "=&r"(value) : "r"(mprv), "r"(p) : "memory" \ ); \ return value; \ } |