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| author | Philipp Hug <philipp@hug.cx> | 2019-02-06 06:48:51 +0100 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2019-02-13 04:49:14 +0000 |
| commit | b09e5001f3071e82ccf7ec64c9cf9a4768d660b1 (patch) | |
| tree | f1a673efd5da4bcd24886b7c049335f52b8c1c75 /src/arch/riscv/ramstage.S | |
| parent | 540a66404591ef41e2581df01647e5788ef0c808 (diff) | |
| download | coreboot-b09e5001f3071e82ccf7ec64c9cf9a4768d660b1.tar.xz | |
riscv: Add initial support for 32bit boards
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
This should probably be changed later.
TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:
util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/ramstage.S')
| -rw-r--r-- | src/arch/riscv/ramstage.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 115a55f290..28183e50e0 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -14,6 +14,7 @@ */ #include <arch/encoding.h> +#include <bits.h> #include <mcall.h> .section ".text._start", "ax", %progbits @@ -27,7 +28,7 @@ _start: slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 |