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author | Nico Huber <nico.h@gmx.de> | 2019-11-04 16:32:01 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-06 13:57:12 +0000 |
commit | c01d0920bb75e0b2849c26421be0a3fac6bc6198 (patch) | |
tree | ec3e2cb63634c8c597dfd2ff1873917b9038a7f9 /src/arch/riscv/romstage.c | |
parent | 214661e00c15f4005fc85ba9bca859fab41ee36c (diff) | |
download | coreboot-c01d0920bb75e0b2849c26421be0a3fac6bc6198.tar.xz |
arch/riscv: Rename `stages.c` to `romstage.c`
It's only used for romstage and is incompatible to ramstages. The latter
get `cbmem_top` passed as a third argument now.
Also drop comments that don't apply to this file anymore.
Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/arch/riscv/romstage.c')
-rw-r--r-- | src/arch/riscv/romstage.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c new file mode 100644 index 0000000000..d5f5a43ce1 --- /dev/null +++ b/src/arch/riscv/romstage.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Entry points must be placed at the location the previous stage jumps + * to (the lowest address in the stage image). This is done by giving + * stage_entry() its own section in .text and placing it first in the + * linker script. + */ + +#include <arch/stages.h> +#include <arch/smp/smp.h> +#include <rules.h> +#include <mcall.h> + +void stage_entry(int hart_id, void *fdt) +{ + HLS()->hart_id = hart_id; + HLS()->fdt = fdt; + smp_pause(CONFIG_RISCV_WORKING_HARTID); + + main(); +} |