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author | Ronald G. Minnich <rminnich@gmail.com> | 2014-11-26 19:25:47 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2014-12-01 19:06:43 +0100 |
commit | e0e784a456c4d64e5e88ce578371fe6c538db559 (patch) | |
tree | 7557a07ab68659eaf81ac50fc860a288055e0845 /src/arch/riscv/romstage.ld | |
parent | 796fe068d3c47f873b82c65cc0591f88f87b0a85 (diff) | |
download | coreboot-e0e784a456c4d64e5e88ce578371fe6c538db559.tar.xz |
Add UCB RISCV support for architecture, soc, and emulation mainboard..
Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/riscv/romstage.ld')
-rw-r--r-- | src/arch/riscv/romstage.ld | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld new file mode 100644 index 0000000000..839c285c41 --- /dev/null +++ b/src/arch/riscv/romstage.ld @@ -0,0 +1,89 @@ +/* + * Memory map: + * + * CONFIG_ROMSTAGE_BASE : text segment + * : rodata segment + * : data segment + * : bss segment + * : stack + * : heap + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add ramstage cross the vga font buffer handling + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +/* + INCLUDE ldoptions + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") +OUTPUT_ARCH(riscv) +INCLUDE ldoptions + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(stage_entry) + +SECTIONS +{ + . = CONFIG_ROMSTAGE_BASE; + + .romtext . : { + _start = .; + *(.text.stage_entry.riscv); + *(.text.startup); + *(.text); + *(.text.*); + } : to_load + + .romdata . : { + *(.rodata); + *(.rodata.*); + *(.machine_param); + *(.data); + *(.data.*); + . = ALIGN(8); + _erom = .; + } + + __image_copy_end = .; + + /* bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + .bss . : { + . = ALIGN(8); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; + } + + _end = .; + + /*preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;*/ + + /* Discard the sections we don't need/want */ + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); + } +} |