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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-16 13:36:47 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-20 20:46:12 +0000 |
| commit | 042a8336f3eb7c7ed4358a100fae23967346e7a2 (patch) | |
| tree | 50751f64e4352cc518b02b6ce9a9c1a388c23f58 /src/arch/riscv/stages.c | |
| parent | b26759d703b636d1462d31cfa38fd3b3d8c90bfe (diff) | |
| download | coreboot-042a8336f3eb7c7ed4358a100fae23967346e7a2.tar.xz | |
arch/riscv: Pass the bootrom-provided FDT to the payload
The RISC-V boot protocol foresees that at every stage boundary (bootrom
to boot loader, boot loader -> OS), register a0 contains the Hart ID and
a1 contains the physical address of the Flattened Device Tree that the
stage shall use.
As a first step, pass the bootrom-provided FDT to the payload,
unmodified.
Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/stages.c')
| -rw-r--r-- | src/arch/riscv/stages.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c index 053fd7634c..80754762bd 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/stages.c @@ -24,9 +24,20 @@ * linker script. */ +#include <arch/boot.h> +#include <arch/encoding.h> #include <arch/stages.h> +#include <rules.h> void stage_entry(void) { + /* + * Save the FDT pointer before entering ramstage, because mscratch + * might be overwritten in the trap handler, and there is code in + * ramstage that generates misaligned access faults. + */ + if (ENV_RAMSTAGE) + rom_fdt = (const void *)read_csr(mscratch); + main(); } |