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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2017-09-29 01:36:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2017-11-07 12:29:27 +0000
commit140a827daa5d878d7b34853dd2b15c64c8d501d1 (patch)
treed65da84f9e4933518ee58af5be99e4b1c9dd06ff /src/arch/riscv/trap_util.S
parent92f0513a0ca8a3d262f3e16f17366a2e517fec74 (diff)
downloadcoreboot-140a827daa5d878d7b34853dd2b15c64c8d501d1.tar.xz
arch/riscv: Drop mret workaround
Our toolchain can compile mret now, and once the encoding changes, we'll have to adjust the code anyway. Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
-rw-r--r--src/arch/riscv/trap_util.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index ae32379562..44cfab7c99 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -141,10 +141,10 @@ supervisor_call_return:
csrr a0, mscratch
restore_regs
# go back into supervisor call
- .word 0x30200073 # mret
+ mret
.global machine_call_return
machine_call_return:
csrr a0, mscratch
restore_regs
# go back into machine call
- .word 0x30200073 # mret
+ mret