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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-01-08 18:31:42 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-20 20:44:43 +0000 |
| commit | 27d34022588717dd5e5f9c309d362b645c2a9ffa (patch) | |
| tree | 895df8d1ac35351b920e9086d6cbe6cfd5590cf3 /src/arch/riscv/trap_util.S | |
| parent | 601197c768ea4a08802016f5b5aae6a9f22a751a (diff) | |
| download | coreboot-27d34022588717dd5e5f9c309d362b645c2a9ffa.tar.xz | |
arch/riscv: Align trap_entry to 4 bytes, as required by spec
The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.
Add the necessary alignment directive before trap_entry.
Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
| -rw-r--r-- | src/arch/riscv/trap_util.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 72a9ae1ced..8aba48b986 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -109,6 +109,7 @@ .text .global trap_entry + .align 2 # four byte alignment, as required by mtvec trap_entry: csrw mscratch, sp |