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| author | Thaminda Edirisooriya <thaminda@google.com> | 2015-09-10 10:55:17 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-09-15 18:04:37 +0000 |
| commit | d9653e1328f8ec07bc1e1fc082f404130c2eee77 (patch) | |
| tree | 894915bf5a1c8e1fcfba9c840234217e6e18848e /src/arch/riscv/trap_util.S | |
| parent | 59598b2e475b50e359c821e35fe1ab60dfce641e (diff) | |
| download | coreboot-d9653e1328f8ec07bc1e1fc082f404130c2eee77.tar.xz | |
riscv-trap-handling: Add functionality, prevent stack corruption
Trap handling code was bugged in that it loaded in the wrong stack
pointer, overwriting the space the processor uses to talk to its host
for doing device requests. Fix this issue, as well as add support for
handling misaligned loads the same way we handle misaligned stores.
Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
| -rw-r--r-- | src/arch/riscv/trap_util.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 9701aaf1f6..274dca6960 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -112,7 +112,7 @@ supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - la sp, 0x80FFF0 + la sp, 0x80FFF0 - 64 1:addi sp,sp,-320 save_tf move a0,sp |