summaryrefslogtreecommitdiff
path: root/src/arch/riscv
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-05 19:56:34 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-09 20:23:41 +0000
commit03026a2a7d4d4b87848e0074efb835306773d16a (patch)
treecb3b1d538bd989df00a03f95525dc4a50649093d /src/arch/riscv
parent445394e9ab6d65317b5394a2a1da3168605f20cf (diff)
downloadcoreboot-03026a2a7d4d4b87848e0074efb835306773d16a.tar.xz
intel/fsp_broadwell_de: Add early timestamps
Modify intel/fsp_broadwell_de such that timestamp_init() is before raminit (and CAR teardown of FSP1.0), adding two new early timestamps while doing so. Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already do it this way. Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35279 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions