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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-06-24 18:15:09 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-28 18:35:03 +0200 |
| commit | 7f72c9b30ec543fc5d485dca5f15790d2c4b03f3 (patch) | |
| tree | cc5cf99611f05bcfb5dc2d9d39ff17ea2ccfb4f1 /src/arch/riscv | |
| parent | 0dde2917a5056bc57cf6da9b2fc41723701b6d41 (diff) | |
| download | coreboot-7f72c9b30ec543fc5d485dca5f15790d2c4b03f3.tar.xz | |
soc/intel/apollolake: Update stage link addresses for 768 KiB cache
Update link addresses for romstage and verstage. Also update FSP-M relocation
address.
BUG=chrome-os-partner:51959
Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15454
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions