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| author | Divya Sasidharan <divya.s.sasidharan@intel.com> | 2015-10-11 11:22:21 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-14 23:09:47 +0100 |
| commit | 1ff0f54f03ed0ebfd4c827bc11e31bc8309828ce (patch) | |
| tree | dfc122a5319e9897122643b2583177b32240fd64 /src/arch/riscv | |
| parent | edb937acd64dbeb6b363ac5e15eb5e2e78469537 (diff) | |
| download | coreboot-1ff0f54f03ed0ebfd4c827bc11e31bc8309828ce.tar.xz | |
soc/braswell: Add CPUID for D0 stepping
Original-Reviewed-on: https://chromium-review.googlesource.com/309122
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://review.coreboot.org/12727
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions