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| author | Duncan Laurie <dlaurie@google.com> | 2018-11-17 12:13:59 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-11-21 01:34:58 +0000 |
| commit | 2aef7f3ceceffecc36c379059335c251e8e2ff3b (patch) | |
| tree | cf01970f529d5701b570da9850372265e5899163 /src/arch/riscv | |
| parent | 3eb720c36e55948c60e158129721705628a9c249 (diff) | |
| download | coreboot-2aef7f3ceceffecc36c379059335c251e8e2ff3b.tar.xz | |
soc/intel/cannonlake: Fix IO decode setup
This change makes the early IO decode setup mirror that of other
Intel SOCs and fixes issues with COM1 not being enabled properly.
Tested by successfully successfully receiving serial output from
an 8250IO UART device at the standard 0x3f8 base address.
Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions