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| author | Furquan Shaikh <furquan@google.com> | 2016-04-27 22:06:47 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-05-02 04:22:53 +0200 |
| commit | 4c76ab678ab892f30c047881c77e64cc3308f85b (patch) | |
| tree | 21c7028d95df206b26264d81905de4e447093e25 /src/arch/riscv | |
| parent | 2a8adac7f544c8e508020132b60bfca1826c56eb (diff) | |
| download | coreboot-4c76ab678ab892f30c047881c77e64cc3308f85b.tar.xz | |
x86/memlayout.h: Do not include data/bss sections in C_ENVIRONMENT_BOOTBLOCK
C_ENVIRONMENT_BOOTBLOCK on x86 is like romstage and uses cache-as-ram
separately. It does not use any data/bss sections.
Change-Id: I8957f467f01e754fa2d95783466a01daa6c4e51a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions