diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-06-21 19:37:03 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-28 18:54:02 +0200 |
| commit | 9d0cce2087139a2eab447aea3fdebfe44e97c280 (patch) | |
| tree | 93463943650d245358dbdcd008abc8e1fcaf55f9 /src/arch/riscv | |
| parent | fefc77afd0e739ec18129f8cd58781e15b9802e4 (diff) | |
| download | coreboot-9d0cce2087139a2eab447aea3fdebfe44e97c280.tar.xz | |
riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler
Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/bootblock.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 07d68ab851..5092ec0405 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -38,10 +38,10 @@ _start: sd t0, 0(t1) la t0, exception_handler - csrw stvec, t0 + csrw mtvec, t0 # clear any pending interrupts - csrwi sip, 0 + csrwi mip, 0 # set up the mstatus register for VM call mstatus_init |