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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-12-11 15:16:30 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-12-18 13:25:45 +0000
commit018a9af4d5867f21ec4a16d606098812ffb8d0b6 (patch)
tree8af31e7432d7e51fcba9d4df4185650a427dcc3e /src/arch/riscv
parent46275faf507dd3a6ca3345425914f4c86c8de3d5 (diff)
downloadcoreboot-018a9af4d5867f21ec4a16d606098812ffb8d0b6.tar.xz
arch/riscv: Don't hardcode CSR numbers anymore
They are hopefully stable enough by now. TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS, with and without this patch, results in the same coreboot.rom. Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/virtual_memory.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index d9bae2aac3..0061847c01 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -59,11 +59,6 @@ void mstatus_init(void)
set_csr(medeleg, delegate);
}
- // Enable all user/supervisor-mode counters using
- // v1.10 register addresses.
- // They moved from the earlier spec.
- // Until we trust our toolchain use the hardcoded constants.
- // These were in flux and people who get the older toolchain
- // will have difficult-to-debug failures.
- write_csr(/*mcounteren*/0x306, 7);
+ // Enable all user/supervisor-mode counters
+ write_csr(mcounteren, 7);
}