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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-11 09:46:03 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-14 10:38:34 +0000 |
| commit | 86d195b192e369eda83035f5c1c2158028d6800b (patch) | |
| tree | cde03f68fd697d45f16ff62008bec1e6e99f4c41 /src/arch/riscv | |
| parent | 63a078e66d3ecb9a8e23c914b5ee6d9e89ef4cf3 (diff) | |
| download | coreboot-86d195b192e369eda83035f5c1c2158028d6800b.tar.xz | |
soc/intel/xeon_sp/skx: Hook up microcode blob
TESTED on ocp/tiagopass: Microcode updates are properly applied (via
FIT). Tested with out of tree patches to report the revision.
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions