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| author | Philipp Hug <philipp@hug.cx> | 2018-10-29 17:55:55 +0100 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-10-30 02:07:58 +0000 |
| commit | d4ab5bbc823b9d764b6f252b11e7b3ed03110d82 (patch) | |
| tree | 7e375f6e5f691a32bfdb355afaaa891195291c70 /src/arch/riscv | |
| parent | bb7f41d85ad8b73b401906426f11e0e6832d3d1e (diff) | |
| download | coreboot-d4ab5bbc823b9d764b6f252b11e7b3ed03110d82.tar.xz | |
src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode
Pointer to opcode increases by unit uint16_t not byte.
Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/29339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/misaligned.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index ba96102839..ebff2d6678 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -160,7 +160,7 @@ static int fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size) static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size) { uint32_t l = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 0); - uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 2); + uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 1); uint32_t ins = (h << 16) | l; if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) { |