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| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-07 14:18:49 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 14:05:10 +0000 |
| commit | 053ea606828afecbabf458beb575272dccdd8a36 (patch) | |
| tree | a71869dd48d0b49e7bfc6a821b793801a18351ea /src/arch/riscv | |
| parent | 15b570b716ff9865fcc942a2c5a0eeeccad1fd1e (diff) | |
| download | coreboot-053ea606828afecbabf458beb575272dccdd8a36.tar.xz | |
soc/intel/denverton_ns: Configure MCA
Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25433
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions