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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-07-07 20:53:29 +0200
committerRonald G. Minnich <rminnich@gmail.com>2016-07-19 20:22:25 +0200
commit1b1d4b7ae653e56ec7cdeec438487ae7ded0e62a (patch)
tree607314dfa772c7721fe1e7f448e30a9c63c15b60 /src/arch/riscv
parent91ef21df62b8dd44c3bfb551a426ed949c5b2eb4 (diff)
downloadcoreboot-1b1d4b7ae653e56ec7cdeec438487ae7ded0e62a.tar.xz
arch/riscv: Enable unaligned load handling
Change-Id: If1c63971335a6e2963e01352acfa4bd0c1d86bc2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15590 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/include/arch/exception.h2
-rw-r--r--src/arch/riscv/trap_handler.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index 28b9279707..fc57b3b55c 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -55,7 +55,7 @@ static inline void exception_init(void)
void trap_handler(trapframe* tf);
void handle_supervisor_call(trapframe* tf);
-void handleMisalignedLoad(trapframe *tf);
+void handle_misaligned_load(trapframe *tf);
void handle_misaligned_store(trapframe *tf);
#endif
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 5b4d0b1801..193be61bdd 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -118,7 +118,7 @@ void trap_handler(trapframe *tf) {
break;
case 4:
printk(BIOS_DEBUG, "Trap: Load address misaligned\n");
- //handleMisalignedLoad(tf);
+ handle_misaligned_load(tf);
break;
case 5:
printk(BIOS_DEBUG, "Trap: Load access fault\n");
@@ -161,7 +161,7 @@ void trap_handler(trapframe *tf) {
while(1);
}
-void handleMisalignedLoad(trapframe *tf) {
+void handle_misaligned_load(trapframe *tf) {
printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
insn_t faultingInstruction = 0;