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| author | Aaron Durbin <adurbin@chromium.org> | 2016-04-19 16:11:22 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-21 20:44:04 +0200 |
| commit | dcee908921444282c82c4cdde455c8819e3965af (patch) | |
| tree | 834311f6fead426c39af46e2cf507a8b2d25e751 /src/arch/riscv | |
| parent | 86cbfa00d00da2786e3a43edd3cf173739f99cba (diff) | |
| download | coreboot-dcee908921444282c82c4cdde455c8819e3965af.tar.xz | |
arch/x86: remove low coreboot table support
In addition to being consistent with all other architectures,
all chipsets support cbmem so the low coreboot table path is
stale and never taken. Also it's important to note the memory
written in to that low area of memory wasn't automatically
reserved unless that path was taken. To that end remove
low coreboot table support for x86.
Change-Id: Ib96338cf3024e3aa34931c53a7318f40185be34c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions