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authorXiang Wang <wxjstz@126.com>2018-08-29 14:59:32 +0800
committerMartin Roth <martinroth@google.com>2018-09-02 03:10:58 +0000
commita5b265bb0ca85cec02c92046904dc0f44f7d6639 (patch)
treef70243b72ff9fca06c9ac27501952fd7c7bf4702 /src/arch/riscv
parent0186912f9ecfc363071affeefa9b9e28966c0245 (diff)
downloadcoreboot-a5b265bb0ca85cec02c92046904dc0f44f7d6639.tar.xz
riscv: separately define stack locations at different stages
BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/include/arch/memlayout.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h
index 9097cf5721..7baab76479 100644
--- a/src/arch/riscv/include/arch/memlayout.h
+++ b/src/arch/riscv/include/arch/memlayout.h
@@ -20,6 +20,20 @@
#define STACK(addr, size) REGION(stack, addr, size, 4096)
+#if defined(__PRE_RAM__)
+ #define CAR_STACK(addr, size) \
+ REGION(car_stack, addr, size, 4K) \
+ ALIAS_REGION(car_stack, stack)
+ #define MEM_STACK(addr, size) \
+ REGION(mem_stack, addr, size, 4K)
+#else
+ #define CAR_STACK(addr, size) \
+ REGION(car_stack, addr, size, 4K)
+ #define MEM_STACK(addr, size) \
+ REGION(mem_stack, addr, size, 4K) \
+ ALIAS_REGION(mem_stack, stack)
+#endif
+
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */