selfboot: remove bounce buffers

Bounce buffers used to be used in those cases where the payload
might overlap coreboot.

Bounce buffers are a problem for rampayloads as they need malloc.

They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig

The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.

For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.

14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)

With this change in place coreboot correctly still loads a bzImage payload.

Werner reports that the 0xe00000 setting works on his broadwell systems.

Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 9 insertions, 2 deletions

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index c85e36a8ea..46e0c2d368 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -80,13 +80,20 @@ config SIPI_VECTOR_IN_ROM
 	default n
 	depends on ARCH_X86
 
+# Set the rambase for systems that still need it, only 5 chipsets as of
+# Sep 2018. This value was 0x100000, chosen to match the entry point
+# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense
+# for as long as we need it; with luck, that won't be much longer.
+# In the long term, both RAMBASE and RAMTOP should be removed.
+# This value leaves more than 1 MiB which is required for fam10
+# and broadwell_de.
 config RAMBASE
 	hex
-	default 0x100000
+	default 0xe00000
 
 config RAMTOP
 	hex
-	default 0x200000
+	default 0x1000000
 	depends on ARCH_X86
 
 # Traditionally BIOS region on SPI flash boot media was memory mapped right below