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authorV Sowmya <v.sowmya@intel.com>2020-12-14 09:22:45 +0530
committerHung-Te Lin <hungte@chromium.org>2020-12-17 06:23:41 +0000
commitf0a9142b24889087a61c66ccf3a39d7a93563e02 (patch)
tree03b9306341e31d96977594aed42144bcfefe387f /src/arch/x86/Kconfig
parent16f213a499a033627a4897f808110759cf3d52fa (diff)
downloadcoreboot-f0a9142b24889087a61c66ccf3a39d7a93563e02.tar.xz
mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543 Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/arch/x86/Kconfig')
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