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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-04 21:08:17 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-07 20:03:55 +0000 |
| commit | b72b5d95286a2290554399e0803d4ba5e7b87f8d (patch) | |
| tree | 8ea86f16a8fffce3650e887ccdc0f8dae0947c96 /src/arch/x86/Kconfig | |
| parent | 3a2660e489d44d29b647e8594e8134e6ee8fc03b (diff) | |
| download | coreboot-b72b5d95286a2290554399e0803d4ba5e7b87f8d.tar.xz | |
arch/x86: Clean up PIRQ_ROUTE
This code is currently only used by via/epia-m850,
it is also somewhat buggy.
Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/x86/Kconfig')
| -rw-r--r-- | src/arch/x86/Kconfig | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 06aadedae6..631d981e45 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -329,3 +329,19 @@ config HAVE_CF9_RESET config HAVE_CF9_RESET_PREPARE bool depends on HAVE_CF9_RESET + +config PIRQ_ROUTE + bool + default n + +config MAX_PIRQ_LINKS + int + default 4 + depends on PIRQ_ROUTE + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_route_irqs will not + function properly, unless this variable is correctly set. |