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authorAaron Durbin <adurbin@chromium.org>2016-03-18 12:21:23 -0500
committerAaron Durbin <adurbin@chromium.org>2016-03-23 14:24:30 +0100
commit7f8afe063139f6fc7076a3e4edf6093a953792dc (patch)
treeb7d0c8d6372abe5b96bc37068e3e132ab97b8ea7 /src/arch/x86/Makefile.inc
parent2b239485358ec063a4803f248c88378076810e24 (diff)
downloadcoreboot-7f8afe063139f6fc7076a3e4edf6093a953792dc.tar.xz
arch/x86: introduce postcar stage/phase
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/arch/x86/Makefile.inc')
-rw-r--r--src/arch/x86/Makefile.inc25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 1ba879573e..10664c3ba3 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -331,6 +331,7 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
+romstage-$(CONFIG_POSTCAR_STAGE) += postcar_loader.c
romstage-y += cbmem.c
romstage-y += boot.c
@@ -390,3 +391,27 @@ rmodules_x86_64-y += memmove.c
endif
endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64
+
+$(eval $(call create_class_compiler,postcar,x86_32))
+postcar-generic-ccopts += -D__POSTCAR__
+
+postcar-y += boot.c
+postcar-y += cbfs_and_run.c
+postcar-y += exit_car.S
+postcar-y += memset.c
+postcar-y += memcpy.c
+postcar-y += memmove.c
+postcar-y += memlayout.ld
+postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
+
+$(objcbfs)/postcar.debug: $$(postcar-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld)
+
+$(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod
+ cp $< $@
+
+cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar
+$(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf
+$(CONFIG_CBFS_PREFIX)/postcar-type := stage
+$(CONFIG_CBFS_PREFIX)/postcar-compression := none