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| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-20 00:56:57 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-24 13:56:00 +0000 |
| commit | 7a7c70b26a9744ec7acac807c98e2aaadd7f422d (patch) | |
| tree | 2821210b8e2a848c40f9db7c6dd87f4b181cc531 /src/arch/x86/Makefile.inc | |
| parent | 4886a6591bf5bc2d3a64f7486101556a29b1320d (diff) | |
| download | coreboot-7a7c70b26a9744ec7acac807c98e2aaadd7f422d.tar.xz | |
arch/x86: prepare for having an idt in other stages
Currently the idt setup and handling is only in ramstage. In
order to prepare having an exception handler in other stages
move the interrupt vector entry code to its own compilation
unit. vec0 and int_hand need to be global so c_start.S
references will resolve at link time.
BUG=b:72728953
Change-Id: I435b96d987d69fb41ea27a73e2dd634b5d6ee3d9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/arch/x86/Makefile.inc')
| -rw-r--r-- | src/arch/x86/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cc529b29cd..b8cf3a6493 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -323,6 +323,7 @@ ramstage-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c +ramstage-y += idt.S ramstage-y += gdt.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memcpy.c |