diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2016-05-26 12:47:05 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-06 04:35:43 +0200 |
commit | 37319036463561521a0ffd613e4c387e65d2ace0 (patch) | |
tree | f8070763ee4b1a068cb89785c101b10c7787e0cf /src/arch/x86/acpi.c | |
parent | d89bcf284111f13ff827bf17f7741e2f5eff2410 (diff) | |
download | coreboot-37319036463561521a0ffd613e4c387e65d2ace0.tar.xz |
acpi: Generate object for coreboot table region
Generate an object to describe the coreboot table region in ACPI
with the HID "CORE0000" so it can be used by kernel drivers.
To keep track of the "CORE" HID usage add them to an enum and add
a function to generate the HID in AML: Name (_HID, "CORExxxx")
BUG=chromium:589817
BRANCH=none
TEST=build and boot on chell, dump SSDT to verify contents:
Device (CTBL)
{
Name (_HID, "CORE0000") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadOnly,
0x7AB84000, // Address Base
0x00008000, // Address Length
)
})
}
Change-Id: I2c681c1fee02d52b8df2e72f6f6f0b76fa9592fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16056
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/x86/acpi.c')
-rw-r--r-- | src/arch/x86/acpi.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 5893461f43..4ebdcbe04d 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -307,6 +307,29 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa) header->checksum = acpi_checksum((void *)tcpa, header->length); } +static void acpi_ssdt_write_cbtable(void) +{ + const struct cbmem_entry *cbtable; + uintptr_t base; + uint32_t size; + + cbtable = cbmem_entry_find(CBMEM_ID_CBTABLE); + if (!cbtable) + return; + base = (uintptr_t)cbmem_entry_start(cbtable); + size = cbmem_entry_size(cbtable); + + acpigen_write_device("CTBL"); + acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); + acpigen_write_name_integer("_UID", 0); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(0, base, size); + acpigen_write_resourcetemplate_footer(); + acpigen_pop_len(); +} + void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); @@ -323,6 +346,10 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) ssdt->length = sizeof(acpi_header_t); acpigen_set_current((char *) current); + + /* Write object to declare coreboot tables */ + acpi_ssdt_write_cbtable(); + { struct device *dev; for (dev = all_devices; dev; dev = dev->next) |