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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/arch/x86/assembly_entry.S
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
downloadcoreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/x86/assembly_entry.S')
-rw-r--r--src/arch/x86/assembly_entry.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 02f492cfaa..4ead9ea769 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -16,7 +16,7 @@
#include <rules.h>
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/*
* This path is for stages that are post bootblock when employing
@@ -43,8 +43,8 @@ _start:
sub %edi, %ecx
rep stosl
-#if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \
- || (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP)))
+#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
+ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
/* Wait for a JTAG debugger to break in and set EBX non-zero */
xor %ebx, %ebx
@@ -55,7 +55,7 @@ debug_spinloop:
#endif
andl $0xfffffff0, %esp
-#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE)
+#if CONFIG(IDT_IN_EVERY_STAGE)
call exception_init
#endif
call car_stage_entry
@@ -75,7 +75,7 @@ car_stage_entry:
#include <arch/x86/prologue.inc>
#include <cpu/x86/32bit/entry32.inc>
#include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
#include <cpu/x86/sse_enable.inc>
#endif