summaryrefslogtreecommitdiff
path: root/src/arch/x86/boot/acpi.c
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2013-04-24 20:59:43 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-05-01 07:12:17 +0200
commitbebf66909a11201a1bbfbdf7f1af40285d76a457 (patch)
treeed037ab4d75d3f35aad545b16433c4219254c4f2 /src/arch/x86/boot/acpi.c
parent243aa44b74935cfc969106dbbe2420ee4a2c39b2 (diff)
downloadcoreboot-bebf66909a11201a1bbfbdf7f1af40285d76a457.tar.xz
x86: use boot state callbacks to disable rom cache
On x86 systems there is a concept of cachings the ROM. However, the typical policy is that the boot cpu is the only one with it enabled. In order to ensure the MTRRs are the same across cores the rom cache needs to be disabled prior to OS resume or boot handoff. Therefore, utilize the boot state callbacks to schedule the disabling of the ROM cache at the ramstage exit points. Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3138 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/x86/boot/acpi.c')
-rw-r--r--src/arch/x86/boot/acpi.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index a3bf718592..3b77caa314 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -637,9 +637,6 @@ void acpi_resume(void *wake_vec)
/* Call mainboard resume handler first, if defined. */
if (mainboard_suspend_resume)
mainboard_suspend_resume();
- /* Tear down the caching of the ROM. */
- if (disable_cache_rom)
- disable_cache_rom();
post_code(POST_OS_RESUME);
acpi_jump_to_wakeup(wake_vec);