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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-07 08:45:17 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-11 19:14:55 +0200 |
| commit | fdc8c8b5fa88494ee5f62572830de10d4187dcce (patch) | |
| tree | 29aa8798b1fae3a96a7a09b916b896eaf8cf0e65 /src/arch/x86/bootblock_crt0.S | |
| parent | 3790a420036874f3d8e01f4f4cf1340f657242d2 (diff) | |
| download | coreboot-fdc8c8b5fa88494ee5f62572830de10d4187dcce.tar.xz | |
arch/x86: Add debug spinloop
Conditionally add a debug spinloop to enable easy connection of JTAG
debuggers.
TEST=Build and run on Galileo Gen2 with a JTAG debugger.
Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15127
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86/bootblock_crt0.S')
| -rw-r--r-- | src/arch/x86/bootblock_crt0.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9fbce5dbb5..8ae82b4368 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -32,6 +32,15 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> +#if IS_ENABLED(CONFIG_BOOTBLOCK_DEBUG_SPINLOOP) + + /* Wait for a JTAG debugger to break in and set EBX non-zero */ + xor %ebx, %ebx + +debug_spinloop: + cmp $0, %ebx + jz debug_spinloop +#endif bootblock_protected_mode_entry: /* Save BIST result */ |