arch/x86: introduce postcar stage/phase

Certain chipsets don't have a memory-mapped boot media
so their code execution for stages prior to DRAM initialization
is backed by SRAM or cache-as-ram. The postcar stage/phase
handles the cache-as-ram situation where in order to tear down
cache-as-ram one needs to be executing out of a backing
store that isn't transient. By current definition, cache-as-ram
is volatile and tearing it down leads to its contents disappearing.
Therefore provide a shim layer, postcar, that's loaded into
memory and executed which does 2 things:

1. Tears down cache-as-ram with a chipset helper function.
2. Loads and runs ramstage.

Because those 2 things are executed out of ram there's no issue
of the code's backing store while executing the code that
tears down cache-as-ram. The current implementation makes no
assumption regarding cacheability of the DRAM itself. If the
chipset code wishes to cache DRAM for loading of the postcar
stage/phase then it's also up to the chipset to handle any
coherency issues pertaining to cache-as-ram destruction.

Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 106 insertions, 0 deletions

diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
new file mode 100644
index 0000000000..e04bd04b25
--- /dev/null
+++ b/src/arch/x86/exit_car.S
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+
+.section ".module_parameters", "aw", @progbits
+/* stack_top indicates the stack to pull MTRR information from. */
+stack_top:
+.long	0
+.long	0
+
+.text
+.global _start
+_start:
+	/* chipset_teardown_car() is expected to disable cache-as-ram. */
+	call	chipset_teardown_car
+
+	/* Enable caching if not already enabled. */
+	mov	%cr0, %eax
+	and	$(~(CR0_CD | CR0_NW)), %eax
+	mov	%eax, %cr0
+
+	/* Ensure cache is clean. */
+	invd
+
+	/* Set up new stack. */
+	mov	stack_top, %esp
+
+	/*
+	 * Honor variable MTRR information pushed on the stack with the
+	 * following layout:
+	 *
+	 * Offset: Value
+	 *   ...
+	 *   0x14: MTRR mask 0 63:32
+	 *   0x10: MTRR mask 0 31:0
+	 *   0x0c: MTRR base 0 63:32
+	 *   0x08: MTRR base 0 31:0
+	 *   0x04: Number of variable MTRRs to set
+	 *   0x00: Number of variable MTRRs to clear
+	 */
+
+	/* Clear variable MTRRs. */
+	pop	%ebx	/* Number to clear */
+	test	%ebx, %ebx
+	jz	2f
+	xor	%eax, %eax
+	xor	%edx, %edx
+	mov	$(MTRR_PHYS_BASE(0)), %ecx
+1:
+	wrmsr
+	inc	%ecx
+	wrmsr
+	inc	%ecx
+	dec	%ebx
+	jnz	1b
+2:
+
+	/* Set Variable MTRRs based on stack contents. */
+	pop	%ebx	/* Number to set. */
+	test	%ebx, %ebx
+	jz	2f
+	mov	$(MTRR_PHYS_BASE(0)), %ecx
+1:
+	/* Write MTRR base. */
+	pop	%eax
+	pop	%edx
+	wrmsr
+	inc	%ecx
+	/* Write MTRR mask. */
+	pop	%eax
+	pop	%edx
+	wrmsr
+	inc	%ecx
+
+	dec	%ebx
+	jnz	1b
+2:
+
+	/* Enable MTRR. */
+	mov	$(MTRR_DEF_TYPE_MSR), %ecx
+	rdmsr
+	/* Make default type uncacheable. */
+	and	$(~(MTRR_DEF_TYPE_MASK)), %eax
+	or	$(MTRR_DEF_TYPE_EN), %eax
+	wrmsr
+
+	/* Load and run ramstage. */
+	call	copy_and_run
+	/* Should never return. */
+1:
+	jmp	1b