diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-09-09 19:09:56 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-08 19:40:40 +0100 |
| commit | b6e97b19ae6a68556838c9801c7824302d72151f (patch) | |
| tree | 0afd66b23e15ca3429134cf061f3ba9e12efc7cd /src/arch/x86/include | |
| parent | 31409617a46c5ac6ef1a893d3c478f76ce4d7d3d (diff) | |
| download | coreboot-b6e97b19ae6a68556838c9801c7824302d72151f.tar.xz | |
Add support for storing POST codes in CMOS
This will use 3 bytes of CMOS to keep track of the POST
code for the current boot while also leaving a record of
the previous boot.
The active bank is switched early in the bootblock.
Test:
1) clear cmos
2) reboot
3) use "mosys nvram dump" to verify that the first byte
contains 0x80 and the second byte contains 0xF8
4) powerd_suspend and then resume
5) use "mosys nvram dump" to verify that the first byte
contains 0x81 and the second byte contains 0xFD
Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/x86/include')
| -rw-r--r-- | src/arch/x86/include/bootblock_common.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index bd1968202f..c9674f4a9c 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -34,3 +34,27 @@ static void sanitize_cmos(void) } } #endif + +#if CONFIG_CMOS_POST +#include <pc80/mc146818rtc.h> + +static void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} +#endif |