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authorSubrata Banik <subrata.banik@intel.com>2019-08-22 11:30:52 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-09-11 14:45:38 +0000
commit8edc6dc91f4a46cca81f99101fb13423615c586a (patch)
tree6d27bec4af66d7304322497b2bf4412235f11c7b /src/arch/x86/include
parentd2496576f1b70ebb2a4e90d525f26be13f6a01f9 (diff)
downloadcoreboot-8edc6dc91f4a46cca81f99101fb13423615c586a.tar.xz
arch/x86: Cache the TSEG region at the top of ram
This patch adds new API for enabling caching for the TSEG region and setting up required MTRR for next stage. BUG=b:140008206 TEST=Build and boot CML-Hatch. Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/arch/x86/include')
-rw-r--r--src/arch/x86/include/arch/romstage.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
index 2ac225875f..15c93f24bd 100644
--- a/src/arch/x86/include/arch/romstage.h
+++ b/src/arch/x86/include/arch/romstage.h
@@ -88,4 +88,13 @@ void run_postcar_phase(struct postcar_frame *pcf);
*/
void late_car_teardown(void);
+/*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+void postcar_enable_tseg_cache(struct postcar_frame *pcf);
+
#endif /* __ARCH_ROMSTAGE_H__ */