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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-09-09 19:09:56 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-08 19:40:40 +0100 |
| commit | b6e97b19ae6a68556838c9801c7824302d72151f (patch) | |
| tree | 0afd66b23e15ca3429134cf061f3ba9e12efc7cd /src/arch/x86/init | |
| parent | 31409617a46c5ac6ef1a893d3c478f76ce4d7d3d (diff) | |
| download | coreboot-b6e97b19ae6a68556838c9801c7824302d72151f.tar.xz | |
Add support for storing POST codes in CMOS
This will use 3 bytes of CMOS to keep track of the POST
code for the current boot while also leaving a record of
the previous boot.
The active bank is switched early in the bootblock.
Test:
1) clear cmos
2) reboot
3) use "mosys nvram dump" to verify that the first byte
contains 0x80 and the second byte contains 0xF8
4) powerd_suspend and then resume
5) use "mosys nvram dump" to verify that the first byte
contains 0x81 and the second byte contains 0xFD
Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/x86/init')
| -rw-r--r-- | src/arch/x86/init/bootblock_simple.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 41f73b43b6..fd9ba2289b 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -10,6 +10,9 @@ static void main(unsigned long bist) #if CONFIG_USE_OPTION_TABLE sanitize_cmos(); #endif +#if CONFIG_CMOS_POST + cmos_post_init(); +#endif } const char* target1 = "fallback/romstage"; |