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author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-06-12 17:30:33 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-17 11:56:01 +0200 |
commit | 2da9524aaf90b6b2f4d7fab81bfc82c9829e3d32 (patch) | |
tree | 54b59f36a0cefd98d8d3286e6bd5bbf7ab3c8609 /src/arch/x86/lib/cpu.c | |
parent | 63a3e1ec7f49222c670d08424cbc7fc7f46ee7b0 (diff) | |
download | coreboot-2da9524aaf90b6b2f4d7fab81bfc82c9829e3d32.tar.xz |
x86 cpu: Allow some cpuid functions during romstage
Allow calls to cpu_phys_address_size and its support functions during
romstage. This enables the proper display of MTRRs during romstage
without duplicating this code.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0
Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277392
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10561
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/x86/lib/cpu.c')
-rw-r--r-- | src/arch/x86/lib/cpu.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 86b5cb0cd4..db7269510b 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -31,12 +31,6 @@ static inline int flag_is_changeable_p(uint32_t flag) return ((f1^f2) & flag) != 0; } -/* Probe for the CPUID instruction */ -int cpu_have_cpuid(void) -{ - return flag_is_changeable_p(X86_EFLAGS_ID); -} - /* * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected * by the fact that they preserve the flags across the division of 5/2. @@ -130,26 +124,6 @@ static const char *cpu_vendor_name(int vendor) return name; } -static int cpu_cpuid_extended_level(void) -{ - return cpuid_eax(0x80000000); -} - -#define CPUID_FEATURE_PAE (1 << 6) -#define CPUID_FEATURE_PSE36 (1 << 17) - -int cpu_phys_address_size(void) -{ - if (!(cpu_have_cpuid())) - return 32; - - if (cpu_cpuid_extended_level() >= 0x80000008) - return cpuid_eax(0x80000008) & 0xff; - - if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) - return 36; - return 32; -} static void identify_cpu(struct device *cpu) { char vendor_name[16]; |