diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-02-28 22:04:51 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-03 23:56:01 +0100 |
| commit | ccd300b4b402167bd1f390ba13378593f1962712 (patch) | |
| tree | 79e8e2592efffa0d1c92f8d40651b74b998be224 /src/arch/x86/memlayout.ld | |
| parent | f8468d43e01c8110bdcb5956106c904b41d1ca09 (diff) | |
| download | coreboot-ccd300b4b402167bd1f390ba13378593f1962712.tar.xz | |
arch/x86: Allow soc/chipset to set linking address
Until recently x86 romstage used to be linked at some default
address. The address itself is not meaningful because the code
was normally relocated at address calculated during insertion
in CBFS. Since some newer SoC run romstage at CAR it became
useful to link romstage code at some address in CAR and avoid
relocation during build/run time altogether.
Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/x86/memlayout.ld')
| -rw-r--r-- | src/arch/x86/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index fb675759c1..5661104179 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -31,14 +31,14 @@ SECTIONS #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ - ROMSTAGE(32M, 1M) + ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) /* Pull in the cache-as-ram rules. */ #include "car.ld" #elif ENV_VERSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ - VERSTAGE(32M, 1M) + VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M) /* Pull in the cache-as-ram rules. */ #include "car.ld" |